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| ltc2950-1/ltc2950-2 1 295012fa features descriptio u applicatio s u turn on debounce en 2v/div pb 10ms/div 2950 ta01b push button on/off controller the ltc ? 2950 is a micropower, wide input voltage range, push button on/off controller. the part contains a push button input with independently programmable on and off debounce times that control the toggling of an open drain enable output. the part also contains a simple micropro- cessor interface to allow for proper system housekeeping prior to power down. under system fault conditions, an internal ? k ? i ? l ? l timer ensures proper power down. the ltc2950 operates over a wide 2.7v to 26v input voltage range to accommodate a wide variety of input power supplies. very low quiescent current (6a typical) makes the ltc2950 ideally suited for battery powered applications. two versions of the part are available to ac- commodate either positive or negative enable polarities. the parts are available in either 8-lead 3mm 2mm dfn or thinsot packages. portable instrumentation meters blade servers portable customer service pda desktop and notebook computers adjustable push button on/off timers low supply current: 6a wide operating voltage range: 2.7v to 26v en output (ltc2950-1) allows dc/dc converter control ? e ? n output (ltc2950-2) allows circuit breaker control simple interface allows graceful p shut down high input voltage ? p ? b pin with internal pull up resistor 10kv esd hbm on ? p ? b input accurate 0.6v threshold on ? k ? i ? l ? l comparator input 8-pin 3mm 2mm dfn and thinsot tm packages v in shdn v in v out en int kill int kill ltc2950-1 ont offt dc/dc buck p/ c 3v ?26v *optional r1 10k 2950 ta01 c ont * 0.033 f c offt * 0.033 f pb gnd v in , lt, ltc and ltm are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. typical applicatio u
ltc2950-1/ltc2950-2 2 295012fa absolute axi u rati gs w ww u electrical characteristics package/order i for atio uu w supply voltage (v in ) ..................................C 0.3v to 33v input voltages ? p ? b ............................................................C 6v to 33v ont ......................................................C 0.3v to 2.7v offt .....................................................C 0.3v to 2.7v ? k ? i ? l ? l .........................................................C 0.3v to 7v output voltages ? i ? ? n ? t .........................................................C 0.3v to 10v en/ ? e ? n ....................................................C 0.3v to 10v (note 1) operating temperature range ltc2950-c1 .............................................. 0c to 70c ltc2950-c2 .............................................. 0c to 70c ltc2950-i1 .......................................... C 40c to 85c ltc2950-i2 .......................................... C 40c to 85c storage temperature range dfn package ..................................... C 65c to 125c tsot-23 ............................................ C 65c to 150c lead temperature (soldering, 10 sec) .................. 300c order part number ddb part* marking t jmax = 125c, ja = 165c/w exposed pad (pin 9) unconnected consult factory for parts speci? ed with wider operating temperature ranges. * the temperature grade is identi? ed by a label on the shipping container. lbkp lbng lbkp lbng t jmax = 125c, ja = 140c/w order part number s8 part* marking ltbkn ltbnf ltbkn ltbnf ltc2950cddb-1 ltc2950cddb-2 ltc2950iddb-1 ltc2950iddb-2 ltc2950cts8-1 ltc2950cts8-2 ltc2950its8-1 ltc2950its8-2 v in 1 pb 2 ont 3 gnd 4 8 kill 7 offt 6 en/en 5 int top view ts8 package 8-lead plastic tsot-23 top view ddb8 package 8-lead ( 3mm 2mm ) plastic dfn 5 6 7 8 9 4 3 2 1 gnd ont pb v in int en/en offt kill the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 2.7v to 26.4v, unless otherwise noted. (note 2) symbol parameter conditions min typ max units v in supply voltage range steady state operation 2.7 26.4 v i in v in supply current system power on, v in = 2.7v to 24v 6 12 a v uvl v in undervoltage lockout v in falling 2.2 2.3 2.4 v v uvl(hyst) v in undervoltage lockout hysteresis 50 300 600 mv order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ ltc2950-1/ltc2950-2 3 295012fa the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 2.7v to 26.4v, unless otherwise noted. (note 2) symbol parameter conditions min typ max units push button pin ( ? p ? b) v ? p ? b(min, max) ? p ? b voltage range single-ended C1 26.4 v i ? p ? b ? p ? b input current 2.5v < v ? p ? b < 26.4v v ? p ? b = 1v v ? p ? b = 0.6v C1 C3 C6 C9 1 C12 C15 a a a v ? p ? b(vth) ? p ? b input threshold ? p ? b falling 0.6 0.8 1 v v ? p ? b(voc) ? p ? b open circuit voltage i ? p ? b = C 1a 1 1.6 2 v debounce timing pins (ont, offt) i ont, offt(pu) ont/offt pull up current v ont, offt = 0v C2.4 C3 C3.6 a i ont, offt(pd) ont/offt pull down current v ont, offt = 1.3v 2.4 3 3.6 a t db, on internal turn on debounce time ont pin float, ? p ? b falling enable asserted 26 32 41 ms t ont additional adjustable turn on time c ont = 1500pf 9 11.5 13.5 ms t db, off internal turn off debounce time offt pin float, ? p ? b falling ? i ? n ? t falling 26 32 41 ms t offt additional adjustable turn off time c offt = 1500pf 9 11.5 13.5 ms p handshake pins ( ? i ? n ? t, ? k ? i ? l ? l) i ? i ? n ? t(lkg) ? i ? n ? t leakage current v ? ? ? i ? n ? t = 3v 1 a v ? i ? n ? t(vol) ? i ? n ? t output voltage low i ? ? ? i ? n ? t = 3ma 0.11 0.4 v v ? k ? i ? l ? l(th) ? k ? i ? l ? l input threshold voltage ? k ? i ? l ? l falling 0.57 0.6 0.63 v v ? k ? i ? l ? l(hyst) ? k ? i ? l ? l input threshold hysteresis 10 30 50 mv i ? k ? i ? l ? l(lkg) ? k ? i ? l ? l leakage current v ? k ? i ? l ? l = 0.6v 0.1 a t ? k ? i ? l ? l(pw) ? k ? i ? l ? l minimum pulse width 30 s t ? k ? i ? l ? l(pd) ? k ? i ? l ? l propagation delay ? k ? i ? l ? l falling enable released 30 s t ? k ? i ? l ? l, on blank ? k ? i ? l ? l turn on blanking (note 3) ? k ? i ? l ? l = low, enable asserted enable released 400 512 650 ms t ? k ? i ? l ? l, off delay ? k ? i ? l ? l turn off delay (note 4) ? k ? i ? l ? l = high, ? ? i ?? ? n ?? ? t asserted enable released 800 1024 1300 ms t en/ ? e ? n, lock out en/ ? e ? n lock out time (note 5) enable released enable asserted 200 256 325 ms i en/ ? e ? n(lkg) en/ ? e ? n leakage current v en/ ? e ? n = 1v, sink current off 0.1 a v en/ ? e ? n(vol) en/ ? e ? n voltage output low i en/ ? e ? n = 3ma 0.11 0.4 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3: the ? k ? i ? l ? l turn on blanking timer period is the waiting period immediately after the enable output is asserted. this blanking time allows suf? cient time for the dc/dc converter and the p to perform power up tasks. the ? k ? i ? l ? l and ? p ? b inputs are ignored during this period. if ? k ? i ? l ? l remains low at the end of this time period, the enable output is released, thus turning off system power. this time delay does not include t db, on or t ont . note 4: the ? k ? i ? l ? l turn off delay is the maximum delay from the initiation of a shutdown sequence ( ? i ? n ? t falling), to the release of the enable output. if the ? k ? i ? l ? l input switches low at any time during this period, enable is released, thus turning off system power. this time is internally ? xed at 1024ms. this time delay does not include t db, off or t offt . note 5: the enable lock out time is designed to allow an application to properly power down such that the next power up sequence starts from a consistent powered down con? guration. ? p ? b is ignored during this lock out time. this time delay does not include t db, on or t ont . electrical characteristics ltc2950-1/ltc2950-2 4 295012fa temperature ( c) ?0 i vin ( a) 10 8 6 4 2 0 ?5 02550 2950 g01 75 100 0 5 10 15 20 25 30 temperature ( c) ?0 ?5 0 25 50 75 100 v in (v) i vin ( a) 10 8 6 4 2 0 2950 g02 2950 g03 ont pull-down current ( a) 1 t db, on + t ont (ms) 100 1000 1000 2950 g04 10 10 100 10000 2950 g05 v in (v) 0 t db, off (ms) 5101520 2950 g06 25 30 2950 g07 2950 g08 v in = 26.4v v in = 3.3v t a = 25 c v in = 3.3v v in = 2.7v t a = 25 c v in (v) 0 0 t db, on (ms) 10 20 30 40 50 5 10 15 20 25 30 t a = 25 c ont external capacitor (nf) 1 t db, off + t offt (ms) 100 1000 1000 10 10 100 10000 t a = 25 c v in = 3.3v offt external capacitor (nf) ?.4 ?.2 ?.0 ?.8 ?.6 v in = 26.4v v in = 2.7v temperature ( c) ?0 ?5 0 25 50 75 100 offt pull-down current ( a) ?.4 ?.2 ?.0 ?.8 ?.6 v in = 26.4v v in = 2.7v 50 40 30 20 10 0 t a = 25 c supply current vs temperature turn on debounce time (t db, on + t ont ) vs ont external capacitor supply current vs supply voltage ont pull-down current vs temperature internal default turn off debounce time (t db, off ) vs v in turn off debounce time (t db, off + t offt ) vs offt external capacitor offt pull-down current vs temperature internal default turn on debounce time (t db, on ) vs v in typical perfor a ce characteristics uw ltc2950-1/ltc2950-2 5 295012fa typical perfor a ce characteristics uw en (v) pb current ( a) 2950 g09 2950 g10 en/en current load (ma) 0 en/en voltage (mv) 500 400 300 200 100 0 8 2950 g11 2 4 6 10 2950 g13 v in (v) 10010 20 30 ? 5 15 25 ?50 ?00 ?50 ?00 ?0 0 pb voltage (v) t a = 25 c v in = 3.3v 0 0 50 100 150 200 250 300 5101520 v in = 3.3v t a = 25 c pb voltage (mv) external pb resistance to ground (k ? ) t a = ?5 c t a = 100 c t a = 25 c v in = 3.3v 04 1 2 3 4 3 2 1 0 t a = 25 c 100k pull-up from en to v in v in (v) 0 en (v) 4 2950 g12 1 2 3 t a = 25 c 100k pull-up from en to v in 1.0 0.8 0.6 0.4 0.2 0 ? p ? b current vs ? p ? b voltage ? p ? b voltage vs external ? p ? b resistance to ground en/ ? e ? n v ol vs current load ? e ? n (ltc2950-2) voltage vs v in en (ltc2950-1) voltage vs v in ltc2950-1/ltc2950-2 6 295012fa v in (pin 1/pin 4): power supply input: 2.7v to 26.4v. ? p ? b (pin 2/pin 3) : push button input. connecting ? p ? b to ground through a momentary switch provides on/off control via the en/ ? e ? n pin. an internal 100k pull-up resis- tor connects to an internal 1.9v bias voltage. the rugged ? p ? b input can be pulled up to 26.4v externally without consuming extra current. ont (pin 3/pin 2): additional adjustable turn on time input. placing an external capacitor to ground determines the additional time (beyond the internal default 32ms) the ? p ? b pin must be held low before the enable output is asserted. floating this pin results in a default turn on debounce time of 32ms. gnd (pin 4/pin 1): device ground. ? i ? n ? t (pin 5/pin 8): open drain interrupt output. after a push button turn-off event is detected, the ltc2950 interrupts the system (p) by bringing the ? i ? n ? t pin low. once the system ? nishes its power down and housekeeping tasks, it sets ? k ? i ? l ? l low, which in turn releases the enable output. if at the end of the power down timer (1024ms) ? k ? i ? l ? l is still high, the enable output is released immediately. ? i ? n ? t may optionally be tied to ? k ? i ? l ? l to release the enable output immediately after the turn-off event has been detected ( ? i ? n ? t = low). en (ltc2950-1, pin 6/pin 7): open drain enable output. this pin is intended to enable system power. en is as- serted high after a valid ? p ? b turn on event. en is released low if: a) ? k ? i ? l ? l is not driven high (by p) within 512ms of the initial valid ? p ? b power turn-on event, b) ? k ? i ? l ? l is driven low during normal operation, c) a second valid ? p ? b event (power turn-off) is detected. the operating range for this pin is 0v to 10v. ?? e ? n (ltc2950-2, pin 6/pin 7) : open drain enable output. this pin is intended to enable system power. ? e ? n is asserted low after a valid ? p ? b turn-on event. ? e ? n releases high if: a) ? k ? i ? l ? l is not driven high (by p) within 512ms of the initial valid ? p ? b power turn-on event, b) ? k ? i ? l ? l is driven low during normal operation, c) a second valid ? p ? b event (power turn-off) is detected. the operating range of this pin is 0v to 10v. offt (pin 7/pin 6): additional adjustable turn off time input. a capacitor to ground determines the additional time (beyond the internal default 32ms) that the ? p ? b pin must be held low before initiating a power down sequence ( ? i ? n ? t falling). floating this pin results in a default turn off time of 32ms. ? k ? i ? l ? l (pin 8/pin 5): ? k ? i ? l ? l input. forcing ? k ? i ? l ? l low releases the enable output. during system turn on, this pin is blanked by a 512ms internal timer to allow the system to pull ? k ? i ? l ? l high. this pin has an accurate 0.6v threshold and can be used as a voltage monitor input. exposed pad (pin 9): exposed pad may be left open or connected to device ground. (tsot-23/dfn) pi fu ctio s uuu ltc2950-1/ltc2950-2 7 295012fa ti i g diagra s w u w kill en/en t kill(pw) t kill(pd) 2950 td01 block diagra w logic oscillator oscillator debounce 2.4v 2.4v 100k v in 2.7v to 26.4v pb gnd en/en kill int ont offt 0.8v 0.6v 2950 bd regulator ltc2950-1/ltc2950-2 8 295012fa ti i g diagra s w u w power on timing power off timing, ? k ? i ? l ? l > 0.6v t db, on t ont pb 16 cycles pb & kill ignored en (ltc2950-1) en (ltc2950-2) t kill, on blank 2950 td02 t db, off t offt pb int offt pb ignored t kill, off delay 2950 td03 16 cycles en (ltc2950-1) en (ltc2950-2) ltc2950-1/ltc2950-2 9 295012fa applicatio s i for atio wu u u description the ltc2950 is a low power (6a), wide input voltage range (2.7v to 26.4v), push button on/off controller that can interface to a p and a power supply. the turn-on and turn-off debounce times are extendable using optional external capacitors. a simple interface ( ? i ? n ? t output, ? k ? i ? l ? l input) allows a system to power on and power off in a controlled manner. turn on when power is ? rst applied to the ltc2950, the part ini- tializes the output pins. any dc/dc converters connected to the en/ ? e ? n pin will therefore be held off. to assert the enable output, ? p ? b must be held low for a minimum of 32ms (t db , on ). the ltc2950 provides additional turn on debounce time via an optional capacitor connected to the ont pin (t ont ). the following equation describes the ad- ditional time that ? p ? b must be held low before asserting the enable output. c ont is the ont external capacitor: c ont = 1.56e-4 [ f/ms] ? (t ont C 1ms) once the enable output is asserted, any dc/dc converters connected to this pin are turned on. the ? k ? i ? l ? l input from the p is ignored during a succeeding 512ms blanking time (t ? k ? i ? l ? l , on blank ). this blanking time represents the maximum time required to power up the dc/dc converter and the p. if ? k ? i ? l ? l is not brought high during this 512ms time window, the enable output is released. the assump- tion is that 512ms is suf? cient time for the system to power up. turn off to initiate a power off sequence, ? p ? b must be held low for a minimum of 32ms (t db , off ). additional turn off debounce time may be added via an optional capacitor connected to the offt pin (t offt ). the following equation describes the additional time that ? p ? b must be held low to initiate a power off sequence. c offt is the offt external capacitor: c offt = 1.56e-4 [ f/ms] ? (t offt C 1ms) once ? p ? b has been validly pressed, ? i ? n ? t is switched low. this alerts the p to perform its power down and housekeeping tasks. the power down time given to the p is 1024ms. note that the ? k ? i ? l ? l input can be pulled low (thereby re- leasing the enable output) at any time after t ? k ? i ? l ? l, on blank period. simpli? ed power on/off sequence figure 1 shows a simpli? ed ltc2950-1 power on and power off sequence. a high to low transition on ? p ? b (t 1 ) initiates the power on sequence. this diagram does not show any bounce on ? p ? b. in order to assert the enable output, the ? p ? b pin must stay low continuously ( ? p ? b high resets timers) for a time controlled by the default 32ms and the external ont capacitor (t 2 Ct 1 ). once en goes high (t 2 ), an internal 512ms blanking timer is started. this blanking timer is designed to give suf? cient time for the dc/dc converter to reach its ? nal voltage, and to allow the p enough time to perform power on tasks. the ? k ? i ? l ? l pin must be pulled high within 512ms of the en pin going high. failure to do so results in the en pin going low 512ms after it went high. (en = low, see figure 2). note that the ltc2950 does not sample ? k ? i ? l ? l and ? p ? b until after the 512ms internal timer has expired. the reason ? p ? b is ignored is to ensure that the system is not forced off while powering on. once the 512ms timer expires (t 4 ), the release of the ? p ? b pin is then debounced with an internal 32ms timer. the system has now properly powered on and the ltc2950 monitors ? p ? b and ? k ? i ? l ? l (for a turnoff command) while consuming only 6a of supply current. a high to low transition on ? p ? b (t 5 ) initiates the power off sequence. ? p ? b must stay low continuously ( ? p ? b high resets debounce timer) for a period controlled by the default 32ms and the external offt capacitor (t 6 Ct 5 ). at the completion of the offt timing (t 6 ), an interrupt ( ? i ? n ? t) is set, signifying that en will be switched low in 1024ms. once a system has ? nished performing its power down operations, it can set ? k ? i ? l ? l low (t 7 ) and thus immediately set en low), terminating the internal 1024ms timer. the release of the ? p ? b pin is then debounced with an internal 32ms timer. the system is now in its reset state: where the ltc2950 is in low power mode (6a). ? p ? b is monitored for a high to low transition. ltc2950-1/ltc2950-2 10 295012fa applicatio s i for atio wu u u figure 1. simpli? ed power on/off sequence for ltc2950-1 figure 2. aborted power on sequence for ltc2950-1 t abort pb kill power on timing en 512ms internal timer t db, on + t ont power turned off 2950 f02 p failed to set kill high t 1 t 2 t db, on t ont t 3 t 4 t 5 t 6 t 7 pb ont offt en kill int pb & kill ignored pb ignored 2950 f01 t kill, on blank t db, off t offt ltc2950-1/ltc2950-2 12 295012fa high voltage pins the v in and ? p ? b pins can operate at voltages up to 26.4v. ? p ? b can, additionally, operate below ground (C 6v) without latching up the device. ? p ? b has an esd hbm rating of 10kv. if the push button switch connected to ? p ? b exhibits high leakage current, then an external pull-up resistor to v in is recommended. furthermore, if the push button switch is physically located far from the ltc2950 ? p ? b pin, parasitic capacitances may couple onto the high impedance ? p ? b input. additionally, parasitic series inductance may cause unpredictable ringing at the ? p ? b pin. placing a 5k resistor from the ? p ? b pin to the push button switch would mitigate parasitic inductance problems. placing a 0.1f capacitor on the ? p ? b pin would lessen the impact of parasitic capaci- tive coupling. applicatio s i for atio wu u u typical applicatio s u voltage monitoring with ? k ? i ? l ? l input the ? k ? i ? l ? l pin can be used as a voltage monitor. figure 5 shows an application where the ? k ? i ? l ? l pin has a dual function. it is driven by a low leakage open drain output of the p. it is also connected to a resistor divider that monitors battery voltage (v in ). when the battery voltage falls below the set value, the voltage at the ? k ? i ? l ? l pin falls below 0.6v and the en pin is quickly pulled low. note that the resistor values should be as large as possible, but small enough to keep leakage currents from tripping the 0.6v ? k ? i ? l ? l comparator. the dc/dc converter shown has an internal pull-up cur- rent on its ? s ? h ? d ? n pin. a pull-up resistor on en is thus not needed. operation without p figure 6 shows how to connect the ? k ? i ? l ? l pin when there is no circuitry available to drive it. the minimum pulse width detected is 30s. if there are glitches on the resis- tor pull-up voltage that are wider than 30s and transition below 0.6v, then an appropriate bypass capacitor should be connected to the ? k ? i ? l ? l pin. figure 5. input voltage monitoring with ? k ? i ? l ? l input figure 6. no p application pb v in shdn v in v out en int kill int kill (open drain) ltc2950-1 gnd ont offt lt1767-3.3 p 9v r1 10k 3.3v 2950 f05 c4 0.1 f r3 806k 1% r2 100k 1% 5.4v threshold *optional v in c ont * 0.033 f c offt * 0.033 f v in shdn v in v out lt1767-3.3 9v 3.3v r1 100k c3* 0.01 f 2950 f06 + c4 0.1 f *optional pb en int kill ltc2950-1 gnd ont offt v in c ont * 0.033 f c offt * 0.033 f ltc2950-1/ltc2950-2 13 295012fa typical applicatio s u power path switching the ? e ? n open drain output of the ltc2950-2 is designed to switch on/off an external power pfet. this allows a user to connect/disconnect a power supply (or battery) to its load by toggling the ? p ? b pin. figure 7 shows the ltc2950-2 controlling a two cell li-ion battery application. the ? i ? n ? t and ? k ? i ? l ? l pins are connected to the output of the pfet through a resistor divider. the ? k ? i ? l ? l pin serves as a voltage monitor. when v out drops below 6v, the ? e ? n pin is open circuited 30s later. v out r1 909k 1% r4 100k 1% c3* 0.1 f 2950 f07 c4 0.1 f ceramic *optional open drain output v th = 0.6v input r5 100k m1 + 4.2v single cell li-ion battery + 4.2v single cell li-ion battery optional glitch filter capacitor v out ,trip point = 6v pb en int kill ltc2950-2 gnd ont offt v in c ont * 0.033 f c offt * 0.033 f pb v in ltc2950-1 gnd ont r6 5k 2950 f08 trace capacitance parasitics c5 0.1 f details omitted for clarity trace inductance noise en int kill offt v in figure 7. power path control with 6v under voltage detect figure 8. noisy ? p ? b trace ? p ? b pin in a noisy environment the rugged ? p ? b pin is designed to operate in noisy envi- ronments. transients below ground (> C6v) and above v in (<30v) will not damage the rugged ? p ? b pin. additionally, the ? p ? b pin can withstand esd hbm strikes up to 10kv. in order to keep external noise from coupling inside the ltc2950, place an r-c network close to the ? p ? b pin. a 5k resistor and a 0.1f capacitor should suf? ce for most noisy applications (see figure 8). ltc2950-1/ltc2950-2 14 295012fa external pull-up resistor on ? p ? b an internal pull-up resistor on the ? p ? b pin makes an ex- ternal pull-up resistor unnecessary. leakage current on the ? p ? b board trace, however, will affect the open circuit voltage on the ? p ? b pin. if the leakage is too large (>2a), the ? p ? b voltage may fall close to the threshold window. to mitigate the effect of the board leakage, a 10k resistor to v in is recommended (see figure 9). typical applicatio s u pb v in ltc2950-1/ ltc2950-2 gnd external board leakage current 100k 2.4v r7 10k 2950 f09 >2 a pins omitted for clarity if external parasitic board leakage >2 a, use external pull-up resistor v in figure 9. external pull-up resistor on ? p ? b pin reverse battery protection to protect the ltc2950 from a reverse battery connec- tion, place a 1k resistor in series with the v in pin (see figure 10). ltc2950-1/ltc2950-2 15 295012fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702) s8 package 8-lead plastic small outline (reference ltc dwg # 05-08-1637) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ?0.05 (ddb8) dfn 0905 rev b 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.50 bsc 1.50 ?1.75 (note 4) 2.80 bsc 0.22 ?0.36 8 plcs (note 3) datum ? 0.09 ?0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.52 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ltc2950-1/ltc2950-2 16 295012fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/lwi 0706 rev a ? printed in usa related parts part number description comments ltc2900 programmable quad supply monitor adjustable ? r ? e ? s ? e ? t, 10-lead msop and 3mm x 3mm dfn packages ltc2904/2905 pin-programmable dual supply monitors adjustable ? r ? e ? s ? e ? t and tolerance, 8-lead sot-23 and 3mm x 2mm dfn packages ltc4411 2.6a low loss ideal diode in thinsot no external mosfet, automatic switching between dc sources ltc4412hv power path controller in thinsot ef? cient diode-oring, automatic switching between dc sources, 3v to 36v ltc4055 usb power controller and li-ion charger automatic switchover, charges 1-cell li-ion batteries v in shdn v out int kill lt1761-1.8 r1 10k r8 1k r5 910k 2950 f10 c4 0.1 f + p 1.8v 9v battery pb en int kill ltc2950-1 gnd ont offt c ont * 0.033 f v in c offt * 0.033 f *optional figure 10. reverse battery protection typical applicatio u |
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